Field of the Invention
The surface of a semiconductor substrate in the production of conventional flash EEPROM memory cells is oxidized locally, i.e., the drain, channel and source regions as wel as the source terminal tracks are left exposed. The gate region is thereafter thermally oxidized and the floating gate is formed on the gate oxide. An insulation layer is formed on the floating gate, and the control-gate electrode is applied over the insulation layer. In that case, the control-gate electrode is used as a word line and it extends over the floating gates of many adjacent memory cells. The memory cells are respectively arranged in pairs along a direction perpendicular to the word lines, such that their drain regions are adjacent and they each have a common drain terminal. The source terminals of all the memory cells are connected to one another by connections parallel to the word lines. That configuration is referred to as a NOR circuit.
In a subsequent production step, the control-gate electrode is used as a mask for doping of the drain and source regions which is self-aligned with respect to this electrode. The distance between the source connections and the word lines, which extend parallel to one another, is thereby determined by the field-oxide edge and the alignment inaccuracies in the production of the word lines.
The distance between the word lines of two adjacent memory cells can be reduced, as suggested in the prior art, in that they are used for the self-aligned implantation of the source regions located between them.
However, the resistance of such a source region and the source connections located between the word lines is relatively high, which renders a memory cell with a poor read characteristic.
An EEPROM in which each cell has its own source and drain region, and a process for the production thereof, is disclosed by U.S Pat. No. 4,513,397 to Ipri et al. There, the surface of the substrate is likewise first locally oxidized, in order to define the position of the individual memory cells. Word lines extend over the channel regions of adjacent memory cells and form the control gates. A polysilicon track, which has an interruption only over a sub-region of the respective channel regions, extends below each of the word lines. A floating electrode, arranged between the word lines and the polysilicon tracks and used for charge storage, extends through the interruption. The word lines and the polysilicon tracks are electrically connected to one another.
German published patent application DE 33 08 092 A1 discloses a memory cell with a floating gate electrode, in which a polysilicon layer is disposed beneath the floating gate electrode. The polysilicon layer has a recess through which the floating gate electrode extends. However, in that case the polysilicon layer is used as a control-gate electrode.
A memory cell with a floating gate having the features according to DE 33 08 092 A1 and U.S. Pat. No. 4,513,397 is also disclosed by the published international application WO 83/03167. There again, the control gate electrodes are formed either by polysilicon tracks underneath the floating gate electrode or by polysilicon regions disposed above and below the floating gate electrode.